The present invention relates to the field of communication systems, and more particularly to a system and method operable to facilitate network clock emulation in a multiple channel environment.
To increase speed and efficiency of information transfer between two or more synchronous communication devices, it is often desirable to convert synchronous communication signals to an asynchronous format, and communicate the information using asynchronous communications links between the synchronous devices. Synchronous networks rely on one or more network clock signals to maintain the order and integrity of the information in the synchronous signals. When the synchronous signals are encoded into asynchronous datagrams, the reference timing information is typically lost. To ultimately deliver the information to synchronous network elements at the receiving end of the asynchronous network, it, therefore, becomes necessary to recreate, or emulate, at the receiving end the network clock signal so that the now asynchronous information can be reformatted into a synchronous form.
Emulating the network clock at customer premises equipmentxe2x80x94such as modems, bridges, and routers coupled to interface devices like telephones and facsimile machinesxe2x80x94can be very complex and expensive in systems supporting a plurality of communication channels serving a plurality of interface devices. Some systems have attempted to implement a separate reference clock for each communication channel served. This technique is expensive and complex.
The present invention recognizes a need for a method and apparatus operable to provide network clock emulation in a multiple channel communication system. In accordance with the present invention, a system and method for providing network clock emulation in a multiple channel environment are provided that substantially reduce or eliminate at least some of the shortcomings associated with prior approaches.
In one aspect of the invention, a method of emulating a network clock signal in a multiple channel environment comprises receiving a plurality of asynchronous signals each associated with one of a plurality of communication channels and storing each of the plurality of asynchronous signals in one of a plurality of buffers, each associated with one of the communication channels, the buffers operable to communicate with a synchronous communication link having a frame rate. The method further comprises identifying one of the plurality of communication channels as a reference channel, determining a current depth of the buffer associated with the reference channel, and altering the frame rate of the synchronous communication link based at least in part on the current depth of the buffer associated with the reference channel.
In another aspect of the present invention, a system for emulating a network clock signal in a multiple channel environment comprises a memory including a plurality of buffers each operable to receive one of a plurality of asynchronous signals. Each signal is operable to be associated with a separate communication channel, wherein at a given time one of the channels comprises a reference channel. The system further comprises a control module operable to communicate with at least some of the plurality of buffers and with a synchronous communication link. The synchronous communication link is operable to communicate the plurality of communication channels at a frame rate. The control module is operable to determine a current depth of the buffer associated with the reference channel and to adjust the frame rate of the synchronous communication link based at least in part on the current depth.
Depending on the specific features implemented, particular embodiments of the present invention may exhibit some, none, or all of the following technical advantages. One aspect of the present invention provides a mechanism for emulating a network clock signal for use with a plurality of communication channels, wherein the emulated network clock signal is generated using a single clock generation device. This aspect of the invention provides an advantage of synchronizing an emulated clock for multiple channels simultaneously, without the need for complex interaction between signal processors, or the use of separate emulated clocks for each channel. In addition, this configuration is easily scalable to any number of communication channels.
In another aspect of the invention, the frame rate of the bus communicating information for transmission across the asynchronous communication links is controlled basedxe2x80x94at least in partxe2x80x94on the depth of a jitter buffer associated with a reference communication channel. Monitoring the frame rate of the synchronous communication link based on feedback relating to the jitter buffer depth provides an effective mechanism for ensuring that the emulated clock accurately tracks the network clock signal. In a particular embodiment, the invention compares a target depth to an average depth of a number of buffer depths to provide an advantage of smoother operation by minimizing the effect of outlying cell delay variations.
In still another aspect of the invention, a mechanism is provided that facilitates switching from a reference channel that is determined to be providing invalid feedback. By changing reference channels in response to detection of invalid feedback, the invention provides an advantage of avoiding erroneous alterations of the emulated clock signal, while maintaining advantages associated with using a reference channel to monitor and control multiple channels in system.
Other technical advantages are readily apparent to one of skill in the art from the attached figures, description, and claims.